Concepedia

Configuration Bitstream Generation Algorithms

Configuration Bitstream Generation Algorithms is a systematic computational method that synthesizes low-level hardware configuration data for programmable devices by encoding design specifications into a structured bitstream format compatible with target architecture constraints.

12

Publications

328

Citations

39

Authors

15

Institutions

Publications per year

2017–2026

2

Parents

Publications

12

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Shang Liu, Wenji Fang, Yao Lu et al. · 2024 · 89 citations

, , +11

Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation

Zheng Ding, Qiang Wu, Yizhong Zhang et al. · Microprocessors and Microsystems · 2013 · 53 citations

, , +14

GeneticFPGA: evolving stable circuits on mainstream FPGA devices

D. Levi, Steven A. Guccione · 2003 · 40 citations

, , +17

Automated extraction of run-time parameterisable cores from programmable device configurations

P. James-Roxby, Steven A. Guccione · 2002 · 35 citations

, , +13

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation

Kostas Siozios, G. Koutroumpezis, K. Tatas et al. · 2005 · 19 citations

, , +17

1–5 of 12

Authors

39

  1. SA
    Steven A. Guccione

    Xilinx (United States), United States

    3 publications · 86 citations

    3

    h-index

  2. MM
    Marco Mattavelli

    École Polytechnique Fédérale de Lausanne, Switzerland

    2 publications · 27 citations

    2

    h-index

  3. SL
    Shang Liu

    Hong Kong University of Science and Technology, Hong Kong SAR China

    1 publications · 89 citations

    1

    h-index

  4. DP
    Danilo Pani

    University of Cagliari, Italy

    1 publications · 17 citations

    1

    h-index

  5. DS
    Dimitrios Soudris

    National Technical University of Athens, Greece

    1 publications · 19 citations

    1

    h-index

1–5 of 39

Institutions

15

  1. Xilinx (United States)

    San Jose, United States

    3 h-index

    5 publications

    137 citations

  2. École Polytechnique Fédérale de Lausanne

    Lausanne, Switzerland

    2 h-index

    4 publications

    54 citations

  3. Chosun University

    Gwangju, South Korea

    1 h-index

    3 publications

    33 citations

  4. University of Hong Kong

    Pok Fu Lam, Hong Kong

    1 h-index

    1 publications

    89 citations

  5. Democritus University of Thrace

    Komotini, Greece

    1 h-index

    5 publications

    95 citations

  6. Institut d'Électronique et des Technologies du numéRique

    Rennes, France

    1 h-index

    1 publications

    10 citations

  7. Institut National des Sciences Appliquées de Rennes

    Rennes, France

    1 h-index

    1 publications

    10 citations

  8. Hong Kong University of Science and Technology

    Hong Kong, Hong Kong

    1 h-index

    6 publications

    534 citations

1–8 of 15

Venues

  1. ARCS Workshops

    Conference · 1 publications · 14 citations

    1

    h-index

  2. Journal of Electronic Testing

    JETTA · 1 publications · 11 citations

    1

    h-index

  3. Journal of Signal Processing Systems

    1 publications · 10 citations

    1

    h-index

  4. Microprocessors and Microsystems

    MICPRO · 1 publications · 53 citations

    1

    h-index

  5. 1

    h-index

1–5