Automated extraction of run-time parameterisable cores from programmable device configurations

Abstract

As FPGA devices have increased in density, the demand for pre-designed logic modules or cores has increased correspondingly. These cores permit reuse of portions of existing designs, reducing the overall design effort. Currently, nearly all cores are specified in some static netlist-oriented format. Such specifications are not well suited for use in a run-time reconfigurable or runtime customizable environment. This paper describes JBitsDiff, a tool constructed using Xilinx's JBits/sup TM/ software, which extracts circuit information directly from configuration bitstreams and produces pre-routed and pre-placed cores suitable for use at run time. Further work to produce parameterizable and reconfigurable cores using JBitsDiff, and some of the pitfalls encountered are also discussed.