Clock Gating Insertion
Clock Gating Insertion is a circuit optimization technique in low-power design that integrates clock gating cells into a synchronous digital circuit to selectively disable the clock signal to idle registers, thereby reducing dynamic power consumption by preventing unnecessary switching activity.
12
Publications
395
Citations
49
Authors
21
Institutions
Publications per year
2017–2026
2
Parents
12
An architectural solution for the inductive noise problem due to clock-gating
Mondira Pant, P. Pant, D. Scott Wills et al. · 1999 · 58 citations
Engineering, Computer Engineering, Electrical Engineering +17
Low‐cost single event double‐upset tolerant latch design
Jianwei Jiang, Yiran Xu, Jiangchuan Ren et al. · Electronics Letters · 2018 · 34 citations
Engineering, Computer Engineering, Electrical Engineering +15
1–5 of 12
49
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1–5 of 49
21
Politecnico di Torino
Turin, Italy
3 h-index
5 publications
217 citations

University of Bologna
Bologna, Italy
2 h-index
2 publications
100 citations
Intel (United States)
Santa Clara, United States
2 h-index
2 publications
73 citations
Kyushu Institute of Technology
Kitakyushu, Japan
1 h-index
1 publications
58 citations

Chinese Academy of Sciences
Beijing, China
1 h-index
6 publications
204 citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
1 h-index
6 publications
72 citations
University of Chinese Academy of Sciences
Beijing, China
1 h-index
6 publications
204 citations
University of Michigan
Ann Arbor, United States
1 h-index
3 publications
45 citations
1–8 of 21
2 publications · 52 citations
2
h-index
Repository · 1 publications · 74 citations
1
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Repository · 1 publications · 17 citations
1
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1 publications · 27 citations
1
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1 publications · 58 citations
1
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1–5