Clock Gating Insertion

Clock Gating Insertion is a circuit optimization technique in low-power design that integrates clock gating cells into a synchronous digital circuit to selectively disable the clock signal to idle registers, thereby reducing dynamic power consumption by preventing unnecessary switching activity.

12

Publications

395

Citations

49

Authors

21

Institutions

Publications per year

2017–2026

2

Authors

49

  1. LB
    Luca Benini

    University of Bologna, Italy

    3 publications · 117 citations

    3

    h-index

  2. PB
    Pietro Babighian

    Politecnico di Torino, Italy

    3 publications · 117 citations

    3

    h-index

  3. EM
    Enrico Macii

    Politecnico di Torino, Italy

    2 publications · 43 citations

    2

    h-index

  4. JO
    Jae-Hyuk Oh

    Massachusetts Institute of Technology, United States

    1 publications · 27 citations

    1

    h-index

  5. VT
    Vivek Tiwari

    Centre for Cellular and Molecular Biology, India

    1 publications · 58 citations

    1

    h-index

1–5 of 49

Venues