Clock Gating In Microprocessors
Clock Gating in Microprocessors is a power optimization technique in digital circuit design that selectively disables the clock signal to idle circuit components, thereby reducing dynamic power consumption by preventing unnecessary switching activity in sequential logic elements.
21
Publications
709
Citations
100
Authors
29
Institutions
Publications per year
2017–2026
1
Parents
21
Deterministic clock gating for microprocessor power reduction
Hai Li, Swarup Bhunia, Y. Chen et al. · 2003 · 102 citations
An architectural solution for the inductive noise problem due to clock-gating
Mondira Pant, P. Pant, D. Scott Wills et al. · 1999 · 58 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 21
100
2
h-index
2
h-index
2
h-index
2
h-index
2
h-index
1–5 of 100
29
Purdue University West Lafayette
West Lafayette, United States
2 h-index
10 publications
800 citations

Harvard University Press
Cambridge, United States
2 h-index
5 publications
125 citations
Intel (United States)
Santa Clara, United States
2 h-index
9 publications
218 citations
IBM (United States)
Armonk, United States
2 h-index
12 publications
501 citations

Chinese Academy of Sciences
Beijing, China
1 h-index
5 publications
205 citations
Intel (Israel)
Kiryat Gat, Israel
1 h-index
3 publications
105 citations
Government Ayurved College, Nanded
Nanded, India
1 h-index
2 publications
200 citations
STMicroelectronics (Italy)
Milan, Italy
1 h-index
1 publications
43 citations
1–8 of 29
2 publications · 77 citations
2
h-index
1 publications · 19 citations
1
h-index
AMR · 1 publications · 10 citations
1
h-index
1 publications · 10 citations
Conference · 1 publications · 11 citations
1–5