Clock Gating In Microprocessors

Clock Gating in Microprocessors is a power optimization technique in digital circuit design that selectively disables the clock signal to idle circuit components, thereby reducing dynamic power consumption by preventing unnecessary switching activity in sequential logic elements.

21

Publications

709

Citations

100

Authors

29

Institutions

Publications per year

2017–2026

1

Authors

100

  1. HL
    Hai Li

    University of Pittsburgh, United States

    2 publications · 160 citations

    2

    h-index

  2. SB
    Swarup Bhunia

    Case Western Reserve University, United States

    2 publications · 160 citations

    2

    h-index

  3. DB
    David Brooks

    Harvard University Press, United States

    2 publications · 57 citations

    2

    h-index

  4. BS
    Balaram Sinharoy

    IBM (United States), United States

    2 publications · 61 citations

    2

    h-index

  5. TN
    T. N. Vijaykumar

    Purdue University West Lafayette, United States

    2 publications · 160 citations

    2

    h-index

1–5 of 100

Venues

  1. 2

    h-index

  2. IEEE Design & Test of Computers

    1 publications · 19 citations

    1

    h-index

  3. Advanced materials research

    AMR · 1 publications · 10 citations

    1

    h-index

1–5