Cache Power Estimation is a computational modeling technique within power estimation that specifically quantifies the dynamic and leakage power consumption of cache memory structures in microprocessors based on their architecture, access patterns, and operational states.
81
Publications
4.9K
Citations
201
Authors
80
Institutions
Publications per year
2017–2026
4
Parents
Publications
81
Amit Sinha, Anantha P. Chandrakasan · 2001 · 359 citations
Analytical energy dissipation models for low-power caches
Milind Kamble, Kanad Ghose · 1997 · 348 citations
1–5 of 81
Authors
201
- FV
8
h-index
- NP
5
h-index
- NG
4
h-index
- ML
4
h-index
- LK
3
h-index
1–5 of 201
Institutions
80
University of California, Riverside
Riverside, United States
8 h-index
17 publications
605 citations
Uppsala University
Uppsala, Sweden
5 h-index
11 publications
216 citations
University of California, Irvine
Irvine, United States
4 h-index
5 publications
381 citations
Northeastern University
Shenyang, China
4 h-index
14 publications
263 citations
Northwestern University
Evanston, United States
4 h-index
7 publications
211 citations
Hewlett-Packard (United States)
Palo Alto, United States
3 h-index
3 publications
634 citations
Harvard University
Cambridge, United States
3 h-index
8 publications
1.1K citations
Pennsylvania State University
State College, United States
3 h-index
17 publications
849 citations
1–8 of 80
Venues
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
4 publications · 158 citations
4
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
4 publications · 249 citations
4
h-index
- Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference · 2 publications · 74 citations
2
h-index
- IEEE Transactions on Computers
2 publications · 42 citations
2
h-index
- IEEE Journal of Solid-State Circuits
2 publications · 884 citations
2
h-index
1–5