Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

TLDR

Future microprocessors will allocate a large fraction of die area to 12–13 kB caches, whose interconnect design—wire models, signaling, routing—critically affects performance, power, and thermal behavior, yet no single analytical tool currently explores all these parameters. This study extends CACTI to enable comprehensive interconnect modeling for large caches. We added support for multiple wire types (RC‑based and differential low‑swing) and non‑uniform cache access, and incorporated state‑of‑the‑art design‑space exploration that accounts for on‑chip network contention and diverse wiring/routing options. Validation of the updated CACTI 6.0 and a case study demonstrate that the tool accurately predicts cache behavior and enhances architectural research.

Abstract

A significant part of future microprocessor real estate will be dedicated to 12 or 13 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire models (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model non-uniform cache access (NUCA). We not only adopt state-of-the-art design space exploration strategies for NUCA, we also enhance this exploration by considering on-chip network contention and a wider spectrum of wiring and routing choices. We present a validation analysis of the new tool (to be released as CACTI 6.0) and present a case study to showcase how the tool can improve architecture research methodologies.