Cache Coherence Interconnects

Cache Coherence Interconnects is a specialized communication architecture that belongs to the class of on-chip interconnects and is distinguished by its support for maintaining consistency among cached copies of shared data across distributed caches in multiprocessor systems.

10

Publications

5.3K

Citations

78

Authors

27

Institutions

Publications per year

2017–2026

3

Authors

78

  1. AC
    Alan Charlesworth

    Oracle (United States), United States

    2 publications · 82 citations

    2

    h-index

  2. JH
    Joel Hestness

    The University of Texas at Austin, United States

    1 publications · 4.9K citations

    1

    h-index

  3. GB
    Gabriel Black

    Google (United States), United States

    1 publications · 4.9K citations

    1

    h-index

  4. PG
    Paolo Gorlani

    Trieste Astronomical Observatory, Italy

    1 publications · 24 citations

    1

    h-index

  5. YY
    Yifan Yuan

    University of Illinois Urbana-Champaign, United States

    1 publications · 25 citations

    1

    h-index

1–5 of 78

Venues

  1. Journal of Parallel and Distributed Computing

    1 publications · 18 citations

    1

    h-index

  2. ACM SIGARCH Computer Architecture News

    1 publications · 4.9K citations

    1

    h-index

  3. Microprocessors and Microsystems

    MICPRO · 1 publications · 24 citations

    1

    h-index

1–3