Bottom-gate Architectures

Bottom-Gate Architecture is a thin-film transistor configuration in which the gate electrode is positioned beneath the semiconductor layer, distinguished from other architectures by the vertical ordering of the gate relative to the source and drain electrodes.

106

Publications

6.9K

Citations

550

Authors

153

Institutions

Publications per year

2017–2026

29

Variants

Bottom-gate Configuration

Authors

550

  1. JJ
    Jin Jang

    Kyung Hee University, South Korea

    4 publications · 198 citations

    4

    h-index

  2. MW
    Man Wong

    Hong Kong University of Science and Technology, Hong Kong SAR China

    3 publications · 77 citations

    3

    h-index

  3. DZ
    Daoben Zhu

    Chinese Academy of Sciences, China

    3 publications · 569 citations

    3

    h-index

  4. TD
    Thomas D. Anthopoulos

    Imperial College London, United Kingdom

    3 publications · 252 citations

    3

    h-index

  5. WH
    Wenping Hu

    Tianjin University, China

    3 publications · 256 citations

    3

    h-index

1–5 of 550

Venues

  1. IEEE Electron Device Letters

    16 publications · 885 citations

    14

    h-index

  2. Applied Physics Letters

    11 publications · 428 citations

    11

    h-index

  3. IEEE Transactions on Electron Devices

    7 publications · 193 citations

    7

    h-index

  4. Journal of Materials Chemistry C

    4 publications · 224 citations

    4

    h-index

  5. ACS Applied Materials & Interfaces

    4 publications · 158 citations

    4

    h-index

1–5