Area-Efficiency Tradeoffs is a design principle in Coarse-Grained Reconfigurable Architectures that characterizes the compromise between the physical resource utilization (area) and computational performance or energy efficiency, guiding architectural decisions to balance hardware complexity against operational effectiveness.
279
Publications
10.4K
Citations
927
Authors
249
Institutions
Publications per year
2017–2026
91
Publications
279
Design tradeoffs for tiled CMP on-chip networks
James Balfour, William J. Dally · 2006 · 507 citations
Fast area-efficient VLSI adders
Tack‐Don Han, David A. Carlson · 1987 · 315 citations
Jason Luu, Ian Kuon, Peter Jamieson et al. · 2009 · 199 citations
1–5 of 279
Authors
927
- JR
12
h-index
- VB
6
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- AY
4
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- MT
4
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- PD
3
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1–5 of 927
Institutions
249
University of Toronto
Toronto, Canada
12 h-index
45 publications
2.8K citations
Nanyang Technological University
Singapore, Singapore
10 h-index
22 publications
762 citations
Stanford University
Stanford, United States
8 h-index
18 publications
2.1K citations
University of Michigan
Ann Arbor, United States
7 h-index
32 publications
1.5K citations
Tsinghua University
Beijing, China
6 h-index
25 publications
883 citations
Intel (United States)
Santa Clara, United States
6 h-index
10 publications
257 citations
IMEC
Leuven, Belgium
6 h-index
22 publications
372 citations
University of Southern California
Los Angeles, United States
6 h-index
13 publications
880 citations
1–8 of 249
Venues
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
19 publications · 762 citations
16
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- IEEE Transactions on Circuits & Systems II Express Briefs
10 publications · 186 citations
10
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- IEEE Transactions on Circuits and Systems I Regular Papers
7 publications · 212 citations
8
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
7 publications · 311 citations
7
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- IEEE Journal of Solid-State Circuits
6 publications · 424 citations
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1–5