Design tradeoffs for tiled CMP on-chip networks

TLDR

The study develops detailed area and energy models for on-chip interconnection networks and investigates how topology, channel width, routing strategy, and buffer size trade off performance, area, and energy efficiency in tiled chip multiprocessors. Using these models, the authors simulate a range of on-chip network designs in an advanced VLSI process, evaluating topology, channel width, routing strategy, and buffer size to assess area and energy efficiency. The results show that adding a second parallel network boosts performance and efficiency, and that a concentrated mesh topology with replicated subnetworks and express channels yields 24 % better area efficiency and 48 % better energy efficiency compared to other evaluated networks.

Abstract

We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency. We simulate the performance of a variety of on-chip networks designed for tiled chip multiprocessors implemented in an advanced VLSI process and compare area and energy efficiencies estimated from our models. We demonstrate that the introduction of a second parallel network can increase performance while improving efficiency, and evaluate different strategies for distributing traffic over the subnetworks. Drawing on insights from our analysis, we present a concentrated mesh topology with replicated subnetworks and express channels which provides a 24% improvement in area efficiency and a 48% improvement in energy efficiency over other networks evaluated in this study.