Y. Wada

Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

S. Maeda, Y. Wada, Kazuya Yamamoto et al. · IEEE Transactions on Electron Devices · 2001 · 16 citations

Engineering, Electrical Engineering, Analog Electronics +16

Development of high voltage, self-healing current limiting element and verification of its operating parameters as a CLD for distribution substations

H. Nakayama, T. Fukazu, Y. Wada et al. · IEEE Transactions on Power Delivery · 1989 · 13 citations

Engineering, Electrical Engineering, Circuit Theory +11

A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

K. Ueda, Koji Nii, Y. Wada et al. · 2002 · 11 citations

Engineering, Electrical Engineering, Low-power Design +15

Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

S. Maeda, Y. Wada, K. Yamamoto et al. · 2002 · 11 citations

Engineering, Electrical Engineering, Microelectronics +16

A 128 kb SRAM with soft error immunity for 0.35 μm SOI-CMOS embedded cell arrays

Y. Wada, Koji Nii, H. Kuriyama et al. · 2002 · 10 citations

Engineering, Computer Engineering, Electrical Engineering +17