Marco Zanuso - Concepedia

Author

Marco Zanuso

Politecnico di Milano

Also Known As

M. Zanuso, Marco Zanuso

Publications

690

Citations

H-Index

Concepts

All Affiliations

Politecnico di Milano University of California, Los Angeles

About

Marco Zanuso is an author at Politecnico di Milano specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	9	9	632
2	Engineering	8	8	366
3	Electrical Engineering	4	4	180
4	Physics	1	1	42
5	Asynchronous Circuits	1	1	25

Marco Zanuso

Publications

669

Citations

H-Index

Page 1

	Year	Citations
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power Davide Tasca, Marco Zanuso, Giovanni Marzin, IEEE Journal of Solid-State Circuits Total Absolute JitterRadio FrequencyAnalog-to-digital ConverterClock RecoveryData Converter	2011	241
Noise Analysis and Minimization in Bang-Bang Digital PLLs Marco Zanuso, Davide Tasca, Salvatore Levantino, IEEE Transactions on Circuits & Systems II Express Briefs Output JitterEngineeringAnalog-to-digital ConverterClock RecoveryHard Nonlinearity	2009	109
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fs<inf>rms</inf> integrated jitter at 4.5mW power Davide Tasca, Marco Zanuso, Giovanni Marzin, Poor Jitter-power CompromiseFractional-n PllElectrical EngineeringEngineeringHigh-frequency Device	2011	88
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL Marco Zanuso, Paolo Madoglio, Salvatore Levantino, IEEE Transactions on Circuits and Systems I Regular Papers Limit CycleAnalog-to-digital ConverterHigh-frequency DeviceClock RecoveryDigital Bang-bang Dll	2009	62
Quantization Effects in All-Digital Phase-Locked Loops Paolo Madoglio, Marco Zanuso, Salvatore Levantino, IEEE Transactions on Circuits & Systems II Express Briefs EngineeringQuantum ComputingPhysicsClock RecoveryData Converter	2007	42
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band Salvatore Levantino, Marco Zanuso, Carlo Samori, Low-power ElectronicsWide Tuning RangeElectrical EngineeringEngineeringVlsi Design	2010	37
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation Marco Zanuso, Salvatore Levantino, Carlo Samori, Electrical EngineeringEngineeringRadio FrequencyHigh-frequency DeviceClock Recovery	2010	30
Time-to-digital converter with 3-ps resolution and digital linearization algorithm Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Electrical EngineeringDigital Linearization AlgorithmEngineeringVlsi DesignClock Recovery	2010	25
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs Carlo Samori, Marco Zanuso, Salvatore Levantino, Adaptive FilterMultipath Adaptive CancellationEngineeringFractional-order SystemMulti-rate Signal Processing	2011	22
Low-Power Divider Retiming in a 3–4 GHz Fractional-N PLL Davide Tasca, Marco Zanuso, Salvatore Levantino, IEEE Transactions on Circuits & Systems II Express Briefs EngineeringVlsi DesignRadio FrequencyHigh-frequency DeviceClock Recovery	2011	13

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