A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fs<inf>rms</inf> integrated jitter at 4.5mW power

Abstract

State-of-the-art digital fractional-N PLLs intended for modern wireless systems make use of high-resolution and high-linearity time-to-digital converters (TDCs) in order to meet the stringent integral phase noise requirements. Those high-performance TDCs complicate the synthesizer design and dissipate large part of the power budget, leading to poor jitter-power compromise. This paper introduces a fractional-N PLL based on a 1b TDC, achieving jitter of 560fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> (from 3kHz to 30MHz) at 4.5mW power consumption, even in the worst-case of fractional spur falling within the PLL bandwidth. The circuit synthesizes frequen cies between 2.92 and 4.05GHz with 70Hz resolution.