Rajeev R. Rao - Concepedia

Concepedia

Author

Rajeev R. Rao

University of Michigan

Also Known As

Rajeev R. Rao, Rajeev Rao

11

Publications

1.6K

Citations

9

H-Index

35

Concepts

All Affiliations

University of Michigan IBM (United States)

RR

About

Rajeev R. Rao is an author at University of Michigan specializing in computer engineering, engineering, and hardware security.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	1.6K
2	Computer Engineering	9	9	1.6K
3	Computer Science	5	5	1.3K
4	Electrical Engineering	5	5	344
5	Asynchronous Circuits	1	1	105

Rajeev R. Rao

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9

Publications

1.6K

Citations

9

H-Index

	Year	Citations
Razor: a low-power pipeline based on circuit-level timing speculation Dan Ernst, Nam Sung Kim, Shidhartha Das, International Symposium on Microarchitecture EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitecturePower Aware Computing	2003	1.1K
Parametric yield estimation considering leakage variability Rajeev R. Rao, Anirudh Devgan, David Blaauw, Precision AgricultureEngineeringVlsi DesignComputer ArchitectureYield Prediction	2004	151
Statistical estimation of leakage current considering inter- and intra-die process variation Rajeev R. Rao, Ashish Srivastava, David Blaauw, Hardware SecurityElectrical EngineeringReliability EngineeringEngineeringProbability Density Function	2003	122
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors Rajeev R. Rao, Kaviraj Chopra, David Blaauw, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Circuit ComplexityEngineeringComputer ArchitectureSoft Error EstimationIntegrated Circuits	2007	105
Soft error reduction in combinational logic using gate resizing and flipflop selection Rajeev R. Rao, David Blaauw, Dennis Sylvester Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design Circuit ComplexitySoft Error ReductionFlipflop Selection MethodEngineeringVlsi Design	2006	73
Leakage-and crosstalk-aware bus encoding for total power reduction H.S. Deogun, Rajeev R. Rao, Dennis Sylvester, Hardware SecurityElectrical EngineeringRuntime LeakageEngineeringVlsi Design	2004	27
Modeling and Analysis of Parametric Yield under Power and Performance Constraints Rajeev R. Rao, David Blaauw, Dennis Sylvester, IEEE Design & Test of Computers EngineeringVlsi DesignEnergy EfficiencyEnergy ConversionYield Prediction	2005	27
Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection Rajeev R. Rao, David Blaauw, Dennis Sylvester Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design Circuit ComplexitySoft Error ReductionFlipflop Selection MethodEngineeringVlsi Design	2006	25
An efficient surface-based low-power buffer insertion algorithm Rajeev R. Rao, David Blaauw, Dennis Sylvester, Hardware SecurityElectrical EngineeringEngineeringVlsi DesignHardware Acceleration	2005	17

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