Rajeev R. Rao

Razor: a low-power pipeline based on circuit-level timing speculation

Dan Ernst, Nam Sung Kim, Shidhartha Das et al. · International Symposium on Microarchitecture · 2003 · 1.1K citations

Engineering, Vlsi Design, Power Optimization (Eda) +16

Parametric yield estimation considering leakage variability

Rajeev R. Rao, Anirudh Devgan, David Blaauw et al. · 2004 · 151 citations

Precision Agriculture, Engineering, Vlsi Design +19

Statistical estimation of leakage current considering inter- and intra-die process variation

Rajeev R. Rao, Ashish Srivastava, David Blaauw et al. · 2003 · 122 citations

Hardware Security, Electrical Engineering, Reliability Engineering +14

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Rajeev R. Rao, Kaviraj Chopra, David Blaauw et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007 · 105 citations

Circuit Complexity, Engineering, Computer Architecture +20

Soft error reduction in combinational logic using gate resizing and flipflop selection

Rajeev R. Rao, David Blaauw, Dennis Sylvester · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 73 citations

Circuit Complexity, Soft Error Reduction, Flipflop Selection Method +19