Kaviraj Chopra - Concepedia

Author

Kaviraj Chopra

University of Michigan

Also Known As

Chopra, Kaviraj, K. Chopra, K. N. Chopra, Kaamil Chopra, Kaviraj Chopra

Publications

1.2K

Citations

H-Index

Concepts

All Affiliations

University of Michigan University of Arizona IBM (United States)Arizona State University Mentor Technologies

About

Kaviraj Chopra is an author at University of Michigan specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	18	18	1.1K
2	Computer Engineering	18	18	1.1K
3	Computer Science	12	12	877
4	Data Science	3	3	422
5	Education	2	2	90

Kaviraj Chopra

Publications

1.1K

Citations

H-Index

Page 1

	Year	Citations
Statistical Timing Analysis: From Basic Principles to State of the Art David Blaauw, Kaviraj Chopra, Ankur Srivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVlsi DesignComputer ArchitectureStatistical Timing AnalysisClock Synchronization	2008	363
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors Rajeev R. Rao, Kaviraj Chopra, David Blaauw, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Circuit ComplexityEngineeringComputer ArchitectureSoft Error EstimationIntegrated Circuits	2007	105
Circuit optimization using statistical static timing analysis Aseem Agarwal, Kaviraj Chopra, David Blaauw, EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitectureHardware Security	2005	75
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation Kaviraj Chopra, Sagar Shah, Ankur Srivastava, International Conference on Computer Aided Design Hardware SecurityElectrical EngineeringEngineeringVlsi DesignCircuit Design	2005	73
Analysis and modeling of CD variation for statistical static timing Brian Cline, Kaviraj Chopra, David Blaauw, Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design EngineeringMeasurementSsta ResultsComputer ArchitectureEducation	2006	67
An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits Rahul Rao, Kaviraj Chopra, David Blaauw, Circuit ComplexityEngineeringVlsi DesignCombinational CircuitsComputer Architecture	2006	61
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation Kaviraj Chopra, S. Shah, Ashish Srivastava, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. Hardware SecurityElectrical EngineeringEngineeringVlsi DesignCircuit Design	2005	44
Circuit optimization using statistical static timing analysis A. Agarwal, Kaviraj Chopra, David Blaauw, Proceedings. 42nd Design Automation Conference, 2005. EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitectureHardware Security	2005	43
Statistical Timing Based Optimization using Gate Sizing A. Agarwal, Kaviraj Chopra, David Blaauw Design, Automation, and Test in Europe	2005	40
A new statistical max operation for propagating skewness in statistical timing analysis Kaviraj Chopra, Bo Zhai, David Blaauw, Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design Hardware SecurityReliability EngineeringEngineeringData ScienceArrival Time Distribution	2006	33

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