Siufu Chiu

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series

Jonathan Chang, Ming Huang, Jonathan Shoemaker et al. · IEEE Journal of Solid-State Circuits · 2007 · 80 citations

Engineering, Memory Design, Emerging Memory Technology +19

A 900MHz UHF RFID Reader Transceiver IC

I. Kipnis, Siufu Chiu, M. Loyer et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2007 · 31 citations

Rf Devices, Engineering, Radio Frequency +11

A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon ® processor

Wei Chen, Szu-Liang Chen, Siufu Chiu et al. · 2013 · 13 citations

Hardware Security, Electrical Engineering, Manycore Processor +15

A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon ® Processor

Jonathan Chang, Szu-Liang Chen, Wei Chen et al. · 2009 · 11 citations

Engineering, Vlsi Design, Computer Architecture +16

The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor

J. Chang, M. Y. Huang, Jonathan Shoemaker et al. · 2006 · 11 citations

Engineering, Memory Design, Computer Architecture +22