Chih-Hsien Chang

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang et al. · 2015 · 29 citations

Engineering, Electrical Engineering, Analog Electronics +13

A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique

Kuo‐Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang · IEEE Journal of Solid-State Circuits · 2011 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 19 citations

Engineering, Communication, Electrical Engineering +17

A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang et al. · IEEE Solid-State Circuits Letters · 2020 · 18 citations · Full text

Engineering, Electrical Engineering, Analog Electronics +16

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao et al. · 2018 · 15 citations

Engineering, Computer Engineering, Electrical Engineering +17