Tsung-Hsien Tsai

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang et al. · 2015 · 29 citations

Engineering, Electrical Engineering, Analog Electronics +13

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 19 citations

Engineering, Communication, Electrical Engineering +17

A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang et al. · IEEE Solid-State Circuits Letters · 2020 · 18 citations · Full text

Engineering, Electrical Engineering, Analog Electronics +16

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang et al. · 2018 · 14 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2021 · 12 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +15