C. Tsai

A double-polysilicon self-aligned npn bipolar process (ADRF) with optional NMOS transistors for RF and microwave applications

K. O, P.M. Garone, C. Tsai et al. · 2002 · 21 citations

Materials Science, Electrical Engineering, Engineering +15

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

K. O, P.M. Garone, C. Tsai et al. · IEEE Transactions on Electron Devices · 1995 · 21 citations

Low-power Electronics, Electrical Engineering, Engineering +14

Physical modeling of the power VDMOST for computer-aided design of integrated circuit

C. Tsai, D.E. Burk, Khai D. T. Ngo · IEEE Transactions on Electron Devices · 1997 · 16 citations

Device Modeling, Electrical Engineering, Power Vdmost +15

A highly manufacturable 0.25 μm multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology

Min-Hua Chang, J.K. Ting, J.S. Shy et al. · 2002 · 12 citations

Engineering, Vlsi Design, Integrated Circuits +16