S. Kakimoto

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Active since

1996

Affiliations

S. Kakimoto is an author at The University of Osaka specializing in metal-oxide-semiconductor field-effect transistors, electrical engineering, and semiconductor devices.

Publications per year

1996–2002

Publications

Hot-carrier-induced degradation of N/sub 2/O-oxynitrided gate oxide NMOSFETs

Toshimasa Matsuoka, Shigenari Taguchi, Hideki Ohtsuka et al. · IEEE Transactions on Electron Devices · 1996 · 38 citations

Engineering, Electrical Engineering, Materials Science +17

Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

Hiroshi Kotaki, S. Kakimoto, M. Nakano et al. · 2002 · 28 citations

Engineering, Electrical Engineering, Low-power Design +14

Ultra low power supply voltage (0.3 V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well

Akira Shibata, Toshimasa Matsuoka, S. Kakimoto et al. · 2002 · 17 citations

Engineering, Electrical Engineering, Microelectronics +15

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