Heonshik Shin

An accurate worst case timing analysis for RISC processors

Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang et al. · IEEE Transactions on Software Engineering · 1995 · 246 citations

Engineering, Timing Schema, Computer Architecture +23

An accurate worst case timing analysis technique for RISC processors

Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang et al. · 1994 · 122 citations

Engineering, Timing Schema, Computer Architecture +24

Scratchpad memory management for portable systems with a memory management unit

Bernhard Egger, Jaejin Lee, Heonshik Shin · 2006 · 59 citations

Non-volatile Memory, Engineering, Computer Architecture +21

Dynamic data scratchpad memory management for a memory subsystem with an MMU

Hyungmin Cho, Bernhard Egger, Jae‐Jin Lee et al. · 2007 · 46 citations

Engineering, Dynamic Data, Computer Architecture +17

Dynamic scratchpad memory management for code in portable systems with an MMU

Bernhard Egger, Jaejin Lee, Heonshik Shin · ACM Transactions on Embedded Computing Systems · 2008 · 45 citations

Engineering, Mmu Memory Page, Actual Memory Access +17