Minkeun Choi

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

A. Mercha, Geert Van der Plas, Victor Moroz et al. · 2010 · 119 citations

Engineering, Computer Engineering, Electrical Engineering +17

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

Wei Guo, Victor Moroz, Geert Van der Plas et al. · 2013 · 35 citations

Engineering, Electrical Engineering, Electronic Materials +16

2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices

S. C. Song, B. Colombeau, Matthias Bauer et al. · 2019 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +15

DTCO Launches Moore’s Law Over the Feature Scaling Wall

Victor Moroz, Xi–Wei Lin, P. Asenov et al. · 2020 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +17

Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime

Weiming Guo, Minkeun Choi, A. Rouhi et al. · 2014 · 19 citations

Engineering, Electrical Engineering, Materials Science +17