Jaehwan Jung

Efficient Parallel Architecture for Linear Feedback Shift Registers

Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2015 · 43 citations

Register Outputs, Engineering, Efficient Parallel Architecture +11

Low-Complexity Tree Architecture for Finding the First Two Minima

Youngjoo Lee, Bongjin Kim, Jaehwan Jung et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2014 · 43 citations

Mathematical Programming, Engineering, Analysis Of Algorithm +16

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory

Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung et al. · IEEE Journal of Solid-State Circuits · 2013 · 31 citations

Engineering, Cbch Decoding, Flash Memory +12

Area-Efficient Multimode Encoding Architecture for Long BCH Codes

Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2013 · 29 citations

Efficient Transformation, Engineering, Weighted-summation-based Multimode Architectures +11

Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems

Jaehwan Jung, In‐Cheol Park · IEEE Communications Letters · 2017 · 24 citations

Hardware Security, Multi-bit Flipping Decoding, Memory Architecture +13