Jihyuck Jo

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks

Jihyuck Jo, Soyoung Cha, Dayoung Rho et al. · IEEE Journal of Solid-State Circuits · 2017 · 65 citations

Convolutional Neural Network, Engineering, Machine Learning +20

Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow

Jihyuck Jo, Suchang Kim, In‐Cheol Park · IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 56 citations

Hardware Security, Rescheduled Dataflow, Engineering +14

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems

Jihyuck Jo, Hoyoung Yoo, In‐Cheol Park · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015 · 52 citations

Energy Consumption, Engineering, Speech Coding +14

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory

Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung et al. · IEEE Journal of Solid-State Circuits · 2013 · 31 citations

Engineering, Cbch Decoding, Flash Memory +12

Area-Efficient Multimode Encoding Architecture for Long BCH Codes

Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2013 · 29 citations

Efficient Transformation, Engineering, Weighted-summation-based Multimode Architectures +11