IEEE Transactions on Circuits & Systems II Express Briefs · 2014 · 44 citations · 9 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureLow-power DesignChannel CodingCoding TheoryDigital Signal ProcessingError Control CodingError-correcting CodesLow-power Digital Circuit DesignArea-efficient DesignDecoder DesignDecoding AlgorithmsDecoding ComplexityLow-density Parity-check CodesParity Check CodesTree Architecture Improvement
This brief presents an area-efficient tree architecture for finding the first two minima as well as the index of the first minimum, which is essential in the design of a low-density parity-check decoder based on the min-sum algorithm. The proposed architecture reduces the number of comparators by reusing the intermediate comparison results computed for the first minimum in order to collect the candidates of the second minimum. As a result, the proposed tree architecture improves the area-time complexity remarkably.
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The Art of Computer Programming
W.J. Worlton · Nuclear Science and Engineering · 1968 · 2.3K citations