Yoshio Matsuda

Twisted bit-line architectures for multi-megabit DRAMs

Hideto Hidaka, K. Fujishima, Yoshio Matsuda et al. · IEEE Journal of Solid-State Circuits · 1989 · 70 citations

Hardware Security, Electrical Engineering, Multi-megabit Drams +15

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Cuong Trinh, Noboru Shibata, Takumi Nakano et al. · 2009 · 69 citations

Non-volatile Memory, Engineering, Technology Scaling +13

The cache DRAM architecture: a DRAM with an on-chip cache memory

Hideto Hidaka, Yoshio Matsuda, M. Asakura et al. · IEEE Micro · 1990 · 59 citations

Engineering, Memory Design, Emerging Memory Technology +18

Scalable shared-buffering ATM switch with a versatile searchable queue

Hisashi Yamanaka, Hideo Saitô, H. Kondoh et al. · IEEE Journal on Selected Areas in Communications · 1997 · 31 citations

Shared-buffering Architecture, Engineering, Vlsi Architecture +15

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector

H. Kondoh, H. Notani, Tsutomu Yoshimura et al. · IEICE Transactions on Electronics · 1995 · 27 citations

Mixed-signal Integrated Circuit, Radio Frequency, High-frequency Device