H. Notani

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

Yutaka Arima, K. Mashiko, Keisuke Okada et al. · IEEE Journal of Solid-State Circuits · 1991 · 54 citations

Engineering, Computer Engineering, Computer Science +15

Scalable shared-buffering ATM switch with a versatile searchable queue

Hisashi Yamanaka, Hideo Saitô, H. Kondoh et al. · IEEE Journal on Selected Areas in Communications · 1997 · 31 citations

Engineering, Computer Engineering, Computer Science +12

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector

H. Kondoh, H. Notani, Tsutomu Yoshimura et al. · IEICE Transactions on Electronics · 1995 · 27 citations

Engineering, Electrical Engineering, Microelectronics +8

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

H. Kondoh, H. Notani, Hisashi Yamanaka et al. · IEEE Journal of Solid-State Circuits · 1993 · 27 citations

Engineering, Computer Engineering, Computer Science +13

A novel power gating scheme with charge recycling

Akira Tada, H. Notani, Masahiro Numa · IEICE Electronics Express · 2006 · 17 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +15