Ryota Sekimoto

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda et al. · IEEE Journal of Solid-State Circuits · 2012 · 46 citations

Tri-level Comparator, Data Converter, Mixed-signal Integrated Circuit +7

A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka et al. · IEEE Journal of Solid-State Circuits · 2013 · 41 citations

Low-power Electronics, Electrical Engineering, Low Threshold Voltage +14

An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014 · 28 citations

Data Converter, Comparator Threshold, Nm Cmos +8

A 40nm 50S/s–8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda et al. · 2011 · 14 citations

Low-power Electronics, Electrical Engineering, Engineering +11

A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro · 2010 · 11 citations

Low-power Electronics, Power Consumption, Electrical Engineering +9