A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro

2010 · 11 citations · 1 references

Concepts

Abstract

This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS process and the simulation results show that the power consumption of quasi differential bootstrapped switch is less than 11nW/MHz at a supply voltage of 0.5V with 10MS/sec. The third order harmonic distortion (HD3) is -104dB with sampling capacitor of 1.28pF.

References

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