J. Harter

Surface induced latchup in VLSI CMOS circuits

D. Takacs, C. Werner, J. Harter et al. · IEEE Transactions on Electron Devices · 1984 · 31 citations

Device Modeling, Electrical Engineering, Engineering +13

Comparison of latch-up in p- and n-well CMOS circuits

D. Takacs, J. Harter, E.P. Jacobs et al. · 1983 · 27 citations

Semiconductors, Semiconductor Technology, Electrical Engineering +14

Design model for bulk CMOS scaling enabling accurate latchup prediction

A.W. Wieder, C. Werner, J. Harter · IEEE Transactions on Electron Devices · 1983 · 26 citations

Hardware Security, Physical Design (Electronics), Engineering +15

Static and transient latchup simulation of VLSI-CMOS with an improved physical design model

M. Strzempa-Depre, J. Harter, C. Werner et al. · IEEE Transactions on Electron Devices · 1987 · 10 citations

Hardware Security, Device Modeling, Electrical Engineering +13