N. Venkateswaran

First-Order Incremental Block-Based Statistical Timing Analysis

C. Visweswariah, Kaushik Ravindran, Kerim Kalafala et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2006 · 226 citations

Hardware Security, Arrival Times, Physical Design (Electronics) +14

Criticality computation in parameterized statistical timing

Jinjun Xiong, Vladimir Zolotov, N. Venkateswaran et al. · 2006 · 63 citations

Criticality Probability, Physical Design (Electronics), Engineering +14

Gate sizing using incremental parameterized statistical timing analysis

Matthew R. Guthaus, N. Venkateswaran, C. Visweswariah et al. · ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. · 2005 · 48 citations

Criticality Probabilities, Electrical Engineering, Physical Design (Electronics) +10

A distributed timing analysis framework for large designs

Tsung‐Wei Huang, Martin D. F. Wong, Debjit Sinha et al. · 2016 · 29 citations

Event-driven Architecture, Engineering, Electronic Design Automation +18

Optimization objectives and models of variation for statistical gate sizing

Matthew R. Guthaus, N. Venkateswaran, Vladimir Zolotov et al. · 2005 · 12 citations

Electrical Engineering, Circuit Analysis, Engineering +13