Concepedia

Ritesh Jhaveri

RJ

8

Publications

1.5K

Citations

8

H-Index

2005

Active since

Affiliations

University of California, Los Angeles(Current)

Intel (United States)

Ritesh Jhaveri is an author at University of California, Los Angeles specializing in engineering, electrical engineering, and microelectronics.

Top concepts

EngineeringMicroelectronicsElectrical EngineeringApplied PhysicsNanoelectronicsElectronic EngineeringVlsi DesignCircuit DesignPower ElectronicsIntegrated Circuits

Publications per year

2005–2014

8

Publications

8

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &#x00B5;m<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 521 citations

-Generation Finfet, Rectangular Fins, Engineering +16

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

Venkatagirish Nagavarapu, Ritesh Jhaveri, Jason C. S. Woo · IEEE Transactions on Electron Devices · 2008 · 357 citations

Novel Tunnel Source, Electrical Engineering, Semiconductor Device +11

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Ritesh Jhaveri, Venkatagirish Nagavarapu, Jason C. S. Woo · IEEE Transactions on Electron Devices · 2010 · 288 citations

Annealing Schemes, Engineering, Vlsi Design +16

Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides

Dimitrios Dimitropoulos, Ritesh Jhaveri, R. Claps et al. · Applied Physics Letters · 2005 · 183 citations · Full text

Photonics, Optical Materials, Engineering +10

Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications

Ritesh Jhaveri, Venkatagirish Nagavarapu, Jason C. S. Woo · IEEE Transactions on Electron Devices · 2008 · 93 citations

Electrical Engineering, Source Soi Mosfet, Engineering +8

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