R. Raina

Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture

N. Tendolkar, R. Raina, R. Woltenberg et al. · 2003 · 77 citations

Engineering, Computer Engineering, Computer Science +12

A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals

Takahiro Yamaguchi, M. Soma, D. Halter et al. · 2002 · 58 citations

Engineering, Computer Engineering, Electrical Engineering +17

Use of DFT techniques in speed grading a 1 GHz+ microprocessor

D. Belete, A. Razdan, Willi Schwarz et al. · 2003 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +11

Functional verification methodology for the PowerPC 604 microprocessor

James Monaco, David Holloway, R. Raina · 1996 · 46 citations

Engineering, Computer Engineering, Computer Science +14

Evaluating ATE features in terms of test escape rates and other cost of test culprits

J. Gatej, Lee Song, C. Pyron et al. · 2003 · 39 citations

Engineering, Computer Engineering, Computer Systems +11