S. Kubouchi

A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer

T. Matano, Y. Takai, T. Takahashi et al. · IEEE Journal of Solid-State Circuits · 2003 · 65 citations

Slew-rate-controlled Output Buffer, Engineering, Vlsi Design +15

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme

Hiroki Fujisawa, S. Kubouchi, Koji Kuroki et al. · IEEE Journal of Solid-State Circuits · 2007 · 19 citations

Low-power Electronics, Electrical Engineering, Multiplexed Data-transfer Scheme +13

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

T. Matano, Mario Morino, M. Nakamura et al. · 2002 · 14 citations

Slew-rate-controlled Output Buffer, Engineering, Vlsi Design +14

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Hironori Fujisawa, M. Nakamura, Y. Takai et al. · IEEE Journal of Solid-State Circuits · 2005 · 12 citations

Hardware Security, Engineering, Vlsi Design +12