Soner Yaldiz

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Bodhisatwa Sadhu, Mark Ferriss, Arun Natarajan et al. · IEEE Journal of Solid-State Circuits · 2013 · 73 citations

Engineering, Electrical Engineering, Analog Electronics +16

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

Mark Ferriss, Jean‐Olivier Plouchart, Arun Natarajan et al. · IEEE Journal of Solid-State Circuits · 2013 · 51 citations

Engineering, Electrical Engineering, Analog Electronics +16

SRAM parametric failure analysis

Jian Wang, Soner Yaldiz, Xin Li et al. · 2009 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +17

Formal verification of phase-locked loops using reachability analysis and continuization

Matthias Althoff, Akshay Rajhans, Bruce H. Krogh et al. · International Conference on Computer Aided Design · 2011 · 35 citations

Engineering, Computer Science, Electrical Engineering +17

Formal verification of phase-locked loops using reachability analysis and continuization

Matthias Althoff, Soner Yaldiz, Akshay Rajhans et al. · 2011 · 32 citations · Full text

Engineering, Computer Science, Electrical Engineering +17