Jyh-Chyurn Guo - Concepedia

Author

Jyh-Chyurn Guo

National Yang Ming Chiao Tung University ORCID

Also Known As

Guo, Jiacheng, J. C. Guo, J.-C. Guo, J.C. Guo, Jiangshuo Guo, Jiating Guo, Jinzhu GUO, Jiongqi Guo, Junbin Guo, Jyh-Chyurn Guo

103

Publications

570

Citations

H-Index

Concepts

All Affiliations

National Yang Ming Chiao Tung University Taiwan Semiconductor Manufacturing Company (Taiwan)National Tsing Hua University Industrial Technology Research Institute

About

Jyh-Chyurn Guo is an author at National Yang Ming Chiao Tung University specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	20	433
2	Electrical Engineering	14	20	433
3	Computer Engineering	10	10	215
4	Applied Physics	7	7	102
5	Physics	2	2	28

Jyh-Chyurn Guo

Publications

448

Citations

H-Index

Page 1

	Year	Citations
A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's Jyh-Chyurn Guo, Sun‐Lin Chung, Chin-Wei Hsu IEEE Transactions on Electron Devices Device ModelingEffective Channel LengthElectrical EngineeringCircuit AnalysisEngineering	1994	58
A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects Jyh-Chyurn Guo, Teng-Yang Tan IEEE Transactions on Electron Devices Conductor Loss EffectsEngineeringScalable ModelPower ElectronicsInterconnect (Integrated Circuits)	2006	45
Pocket Implantation Effect on Drain Current Flicker Noise in Analog nMOSFET Devices Jincheng Wu, Chao Cheng, Kai Ling Chiu, IEEE Transactions on Electron Devices Low-power ElectronicsElectrical EngineeringPocket Implantation EffectPocket Implant RegionPocket Implantation	2004	35
Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs Kuo-Liang Yeh, Jyh-Chyurn Guo IEEE Transactions on Electron Devices Electrical EngineeringEngineeringRf Noise ParametersRf SemiconductorHigh-frequency Device	2012	29
A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization C.H. Chen, Chia-He Chang, C.P. Chao, Foundry Soc TechnologyPassive ElementsFoundry 90EngineeringSuperb 185	2004	29
A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling Jyh-Chyurn Guo, Yi-Min Lin IEEE Transactions on Electron Devices EngineeringRadio FrequencyAnalog DesignInterconnect (Integrated Circuits)Electromagnetic Compatibility	2006	28
0.13-&lt;tex&gt;$muhbox m$&lt;/tex&gt;RF CMOS and Varactors Performance Optimization by Multiple Gate Layouts Chih-Chao Ho, Chang-Hsin Kuo, Y.-J. Chan, IEEE Transactions on Electron Devices Low-power ElectronicsElectrical EngineeringCmos DevicesEngineeringVlsi Design	2004	24
A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs Kuo-Liang Yeh, Jyh-Chyurn Guo IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringPhysical Design (Electronics)EngineeringAdvanced Packaging (Semiconductors)	2011	21
A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs Jyh-Chyurn Guo, Yi-Min Lin IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Device ModelingElectrical EngineeringEngineeringRf SemiconductorHigh-frequency Device	2008	18
A Broadband and Scalable On-Chip Inductor Model Appropriate for Operation Modes of Varying Substrate Resistivities Jyh-Chyurn Guo, Teng-Yang Tan IEEE Transactions on Electron Devices EngineeringScalable ModelPower ElectronicsInterconnect (Integrated Circuits)Electromagnetic Compatibility	2007	17

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