Yesin Ryu

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

Chi Sung Oh, Ki Chul Chun, Young-Yong Byun et al. · 2020 · 68 citations

Engineering, Computer Engineering, Computer Science +17

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

Ki Chul Chun, Yong Ki Kim, Yesin Ryu et al. · IEEE Journal of Solid-State Circuits · 2020 · 47 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features

Yesin Ryu, Sung-Gi Ahn, Jae‐Hoon Lee et al. · IEEE Journal of Solid-State Circuits · 2023 · 41 citations

Engineering, Computer Engineering, Computer Science +17

HBM3 RAS: Enhancing Resilience at Scale

Sudhanva Gurumurthi, Ki-Jun Lee, Munseon Jang et al. · IEEE Computer Architecture Letters · 2021 · 24 citations

Engineering, Computer Engineering, Computer Science +15

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Ki Chul Chun, Yong-Gyu Chu, Jin‐Seok Heo et al. · 2018 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17