Mark Nakamoto

Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Xiaoxia Wu, Wei Zhao, Mark Nakamoto et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010 · 42 citations

Engineering, Vlsi Design, Computer Architecture +16

TechTuning: Stress Management For 3D Through-Silicon-Via Stacking Technologies

Riko Radojcic, Matt Nowak, Mark Nakamoto · AIP conference proceedings · 2011 · 13 citations

Engineering, Industrial Engineering, Mechanical Engineering +17

Simulation methodology and flow integration for 3D IC stress management

Mark Nakamoto, Riko Radojcic, Wei Zhao et al. · 2010 · 13 citations

Engineering, Electronic Design Automation, Computer Architecture +20

Design for manufacturability for fabless manufactuers

Riko Radojcic, Dan Perry, Mark Nakamoto · IEEE Solid-State Circuits Magazine · 2009 · 12 citations

Engineering, Accelerated Design, Industrial Engineering +19

Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations

Dan Perry, Mark Nakamoto, Nishath Verghese et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 10 citations

Engineering, Electrical Dfm Methodology, Industrial Engineering +25