D.H. Lee

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

T. Park, Siyoung Choi, D.H. Lee et al. · 2004 · 93 citations

Engineering, Integrated Circuits, Nanocomputing +17

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

Hye Jip Cho, Kwangyou Seo, Won-Cheol Jeong et al. · 2011 · 24 citations

Engineering, Vlsi Design, Integrated Circuits +19

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

R.-H. Kim, B.H. Kim, Takanori Matsuda et al. · 2014 · 18 citations

Engineering, Vlsi Design, Computer Architecture +18

Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate

D.H. Lee, Kyongsik Yeom, M.H. Cho et al. · 2002 · 13 citations

Materials Engineering, Pmos Transistors, Electrical Engineering +11

Pseudo-breakdown events induced by biased-thermal-stressing of intra-level Cu interconnects-reliability and performance impact

W.S. Song, T.J. Kim, D.H. Lee et al. · 2003 · 11 citations

Rc Delay Simulation, Engineering, Interconnect (Integrated Circuits) +17