K. Itabashi

600 V JEDEC-qualified highly reliable GaN HEMTs on Si substrates

T. Kikkawa, Tsutomu Hosoda, Kenji Imanishi et al. · 2014 · 46 citations

Engineering, Electrical Engineering, Materials Science +17

A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture

M. Matsumiya, S. Kawashima, M. Sakata et al. · IEEE Journal of Solid-State Circuits · 1992 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +16

A split wordline cell for 16 Mb SRAM using polysilicon sidewall contacts

K. Itabashi, Keisuke Mizutani, T. Koga et al. · 2002 · 16 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus

M. Matsumiya, Shuichi Kawashima, M. Sakata et al. · 2003 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +16

Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM

K. Itabashi, Shinji Tsuboi, Hiroyuki Nakamura et al. · 1997 · 13 citations

Engineering, Electrical Engineering, Materials Science +13