Vassilios Gerousis

Pin-3D

Sai Pentapati, Kyungwook Chang, Vassilios Gerousis et al. · 2020 · 24 citations

3D Ic Architecture, Rc Scaling, Physical Design (Electronics) +10

Impact of a SADP flow on the design and process for N10/N7 metal layers

Werner Gillijns, S. M. Yasser Sherazi, Darko Trivković et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2015 · 22 citations

Engineering, Mechanical Engineering, Computer-aided Design +27

Low track height standard cell design in iN7 using scaling boosters

S. M. Yasser Sherazi, C.M. Jha, Dimitrios Rodopoulos et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2017 · 19 citations

Low-power Electronics, Standard Cell Design, Electrical Engineering +14

Design and modeling challenges for 90 NM and 50 NM

Vassilios Gerousis · 2004 · 17 citations

Engineering, Vlsi Design, Electronic Design +23

Demonstrating production quality multiple exposure patterning aware routing for the 10NM node

Lars W. Liebmann, Vassilios Gerousis, Paul Gutwin et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2014 · 17 citations

Technology Node, Engineering, Electronic Design Automation +16