Tapas Dutta

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation

Girish Pahwa, Tapas Dutta, Sourabh Khandelwal et al. · IEEE Transactions on Electron Devices · 2016 · 168 citations

Device Modeling, Negative Capacitance Fet, Electrical Engineering +15

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Girish Pahwa, Tapas Dutta, Sourabh Khandelwal et al. · IEEE Transactions on Electron Devices · 2016 · 139 citations

Device Modeling, Negative Capacitance Fet, Electrical Engineering +10

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

Girish Pahwa, Tapas Dutta, Yogesh Singh Chauhan · IEEE Transactions on Electron Devices · 2018 · 126 citations

Horizontal Electric Field, Hysteresis Regimes, Engineering +19

Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

Girish Pahwa, Tapas Dutta, Yogesh Singh Chauhan · IEEE Transactions on Electron Devices · 2017 · 114 citations

Device Modeling, External Biases, Electrical Engineering +14

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

Tapas Dutta, Girish Pahwa, Amit Ranjan Trivedi et al. · IEEE Electron Device Letters · 2017 · 89 citations

Non-volatile Memory, Electrical Engineering, Reference Finfets +13