Tapas Dutta

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation

Girish Pahwa, Tapas Dutta, Sourabh Khandelwal et al. · IEEE Transactions on Electron Devices · 2016 · 169 citations

Engineering, Electrical Engineering, Circuit Theory +16

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Girish Pahwa, Tapas Dutta, Sourabh Khandelwal et al. · IEEE Transactions on Electron Devices · 2016 · 139 citations

Engineering, Electrical Engineering, Circuit Theory +16

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

Girish Pahwa, Tapas Dutta, Yogesh Singh Chauhan · IEEE Transactions on Electron Devices · 2018 · 128 citations

Engineering, Electrical Engineering, Materials Science +17

Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

Girish Pahwa, Tapas Dutta, Yogesh Singh Chauhan · IEEE Transactions on Electron Devices · 2017 · 116 citations

Engineering, Electrical Engineering, Physics +17

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

Tapas Dutta, Girish Pahwa, Amit Ranjan Trivedi et al. · IEEE Electron Device Letters · 2017 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17