Ilias Chlis

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

Jay Im, Kevin Zheng, Chuen-Huei Adam Chou et al. · IEEE Journal of Solid-State Circuits · 2020 · 111 citations

7-Nm Finfet Cmos, Clock Recovery, Data Converter +6

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET

Jay Im, Kevin Zheng, Adam Chou et al. · 2020 · 83 citations

Engineering, Vlsi Design, Clock Recovery +8

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET

James Hudner, Declan Carey, Ronan Casey et al. · 2018 · 35 citations

Continuous-time Linear Equalizers, Capacitance Buffer, Data Converter +6

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Ilias Chlis, Domenico Pepe, Domenico Zito · International Journal of Circuit Theory and Applications · 2015 · 22 citations · Full text

Transformer-Based Input Integrated Matching in Cascode Amplifiers: Analytical Proofs

Domenico Pepe, Ilias Chlis, Domenico Zito · IEEE Transactions on Circuits and Systems I Regular Papers · 2017 · 22 citations

Circuit Topology, Electrical Engineering, Rf Subsystem +11