Robert M. Radway - Concepedia

Author

Robert M. Radway

Stanford University ORCID

Also Known As

B.Q. Le, R. M. Radway, R.M. Radway, Radway, Robert, Radway, Robert M., Robert M. Radway, Robert Radway

Publications

420

Citations

H-Index

Concepts

All Affiliations

Stanford University Taiwan Semiconductor Manufacturing Company (Taiwan)San Jose State University Meta (United States)Menlo School

About

Robert M. Radway is an author at Stanford University specializing in computer engineering, computer architecture, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	277
2	Computer Engineering	8	8	277
3	Computer Science	7	7	247
4	Electrical Engineering	3	3	99
5	Natural Sciences	1	1	19

Robert M. Radway

Publications

320

Citations

H-Index

Page 1

	Year	Citations
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference Kartik Prabhu, Albert Gural, Zainab F. Khan, IEEE Journal of Solid-State Circuits EngineeringMachine LearningHardware AlgorithmComputer ArchitectureHardware Systems	2022	60
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference Massimo Giordano, Kartik Prabhu, Kalhan Koul, EngineeringMachine LearningHardware AlgorithmComputer ArchitectureHigh-performance Architecture	2021	48
RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays Binh Le, Akash Levy, Tony F. Wu, IEEE Transactions on Electron Devices Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureHardware Systems	2021	36
14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques Tony F. Wu, Binh Le, Robert M. Radway, Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureMs Latency	2019	33
Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array E. R. Hsieh, Xin Zheng, Binh Le, IEEE Electron Device Letters Non-volatile MemoryElectrical EngineeringSet/reset EnduranceEngineeringEmerging Memory Technology	2021	30
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications Lita Yang, Robert M. Radway, Yu‐Hsin Chen, IEEE Micro EngineeringHardware AlgorithmComputer ArchitectureIntegrated CircuitsAr/vr Applications	2022	27
Illusion of large on-chip memory by networked computing chips for neural network inference Robert M. Radway, Andrew Bartolo, Paul C. Jolly, Nature Electronics EngineeringComputational NeuroscienceNeurocomputersLarge On-chip MemoryComputer Architecture	2021	24
The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design Robert M. Radway, Khushal Sethi, W.-C. Chen, 2021 IEEE International Electron Devices Meeting (IEDM) EngineeringExecution Time BenefitsComputer Architecture3D ModelingComputer-aided Design	2021	19
8-bit Transformer Inference and Fine-tuning for Edge Accelerators Jeffrey Yu, Kartik Prabhu, Yonatan Urman,	2024	16
Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM Tathagata Srimani, A. C. Yu, Robert M. Radway,	2023	15

Page 1