Naga Sasidhar

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Rajesh Inti, Wenjing Yin, Amr Elshazly et al. · IEEE Journal of Solid-State Circuits · 2011 · 76 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

Sachin Rao, Brian Young, Amr Elshazly et al. · 2011 · 70 citations

Engineering, Electrical Engineering, Analog Electronics +16

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback

Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi et al. · IEEE Journal of Solid-State Circuits · 2009 · 34 citations

Engineering, Electrical Engineering, Analog Electronics +12

A Distortion Compensating Flash Analog-to-Digital Conversion Technique

Vaishnav Srinivas, Shanthi Pavan, Ashish Lachhwani et al. · IEEE Journal of Solid-State Circuits · 2006 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

Rajesh Inti, Wenjing Yin, Amr Elshazly et al. · 2011 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +16