Statistics
Publications
1
Citations
15
H-Index
1
Active since
1995
Affiliations
AT&T (United States)(Current)
J. W. Bailey is an author at AT&T (United States) specializing in very-large-scale integration layout, integrated circuit design, and semiconductor devices.
Publications per year
1995–1995
1
1
<title>Reduction of ASIC gate-level line-end shortening by mask compensation</title>
Joseph G. Garofalo, John J. DeMarco, J. W. Bailey et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1995 · 15 citations
Engineering, Computer Engineering, Electrical Engineering +10
1–1 of 1