<title>Reduction of ASIC gate-level line-end shortening by mask compensation</title>

Abstract

One of the most dramatic effects that one encounters when attempting the optical imaging of 0.5 k ASIC gate levels is the truncation or shortening of transistor geometries. This reduces the wafer process latitude and in some cases even eliminates the level-to-level overlay margin. We investigate a number of techniques, including various complexities of mask compensation and modified illumination to mitigate this phenomenon in manners sufficiently general to accommodate ASIC layouts.