Daiki Hirabayashi

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi et al. · 2012 · 18 citations

Phase Blending, Engineering, Gated Phase +12

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi et al. · Journal of Electronic Testing · 2013 · 17 citations

Engineering, Improved Linearity, Vlsi Architecture +5

Phase noise measurement techniques using delta-sigma TDC

Yusuke Osawa, Daiki Hirabayashi, Naohiro Harigai et al. · 2014 · 14 citations

Engineering, Small Phase Noise, Analog-to-digital Converter +14

Experimental verification of timing measurement circuit with self-calibration

T. Chujo, Daiki Hirabayashi, Congbing Li et al. · 2014 · 11 citations

Experimental Verification, Engineering, Vlsi Design +19