Abbas Sheibanyrad

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad · 2006 · 83 citations

Dspin Architecture, Engineering, High Performance Computer Network +17

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Abbas Sheibanyrad, Alain Greiner, Ivan Miro-Panades · IEEE Design & Test of Computers · 2008 · 60 citations

System On Chip, Distributed Noc, Engineering +14

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture

Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner · Design, Automation, and Test in Europe · 2007 · 35 citations

Cluster Computing, Engineering, Computer Architecture +21

A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

Pascal Vivet, Yvain Thonnart, R. Lemaire et al. · IEEE Journal of Solid-State Circuits · 2016 · 32 citations

Network-on-chip Circuit, Engineering, Vlsi Design +18

Two efficient synchronous asynchronous converters well-suited for networks-on-chip in GALS architectures

Abbas Sheibanyrad, Alain Greiner · Integration · 2007 · 29 citations

System On Chip, Electrical Engineering, Engineering +11