A. Makihara

Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

A. Makihara, M. Midorikawa, Tatsuya Yamaguchi et al. · IEEE Transactions on Nuclear Science · 2005 · 52 citations

Hardware Security, Low-power Electronics, Electrical Engineering +14

Analysis of single-ion multiple-bit upset in high-density DRAMs

A. Makihara, H. Shindou, Norio Nemoto et al. · IEEE Transactions on Nuclear Science · 2000 · 48 citations

Electrical Engineering, Engineering, Physics +10

Optimization for SEU/SET Immunity on 0.15 $\mu$m Fully Depleted CMOS/SOI Digital Logic Devices

A. Makihara, Tatsuya Yamaguchi, H. Asai et al. · IEEE Transactions on Nuclear Science · 2006 · 27 citations

Electrical Engineering, Engineering, Vlsi Design +9

Single-event effects in 0.18 /spl mu/m CMOS commercial processes

A. Makihara, Y. Sakaide, Y. Tsuchiya et al. · IEEE Transactions on Nuclear Science · 2003 · 22 citations

Event-driven Architecture, Engineering, Vlsi Design +16

DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process

Akifumi Maru, H. Shindou, T. Ebihara et al. · IEEE Transactions on Nuclear Science · 2010 · 19 citations

Engineering, Vlsi Design, Computer Architecture +17